In U.S. Pat. No. 5,513,318 assigned to the assignee of the present invention, a technique is disclosed for accomplishing the "built-in" self-testing (BIST) of first-in, first-out (FIFO) memory units employing ring counter accessing of static random access memory units (SRAM)s. Sequences of operations are performed on the memory unit under test to detect faults associated with the read-out of spurious data in the presence and absence of real data having been stored in the memory, the ability to accept read and write commands, the resetting of the read and write access registers simultaneously and independently, etc., including alteration of various flag signals normally set or unset to indicate proper memory operation. While the arrangement described in the above-mentioned patent operates satisfactorily, it would be advantageous to achieve a self-testing ability for memory units other than FIFO memories and, in particular, to dynamic random access memories (DRAM)s.
A DRAM differs from an SRAM in the technology of the memory cell employed for the storage of binary information. Basically, the SRAM uses a flip-flop in each memory cell which remains indefinitely in the state to which it has been set. The DRAM memory cell employs a capacitor to store a charge whose value must periodically be refreshed because the charge tends to leak-off with time. Typically, an SRAM requires approximately 6 transistors per memory cell while a DRAM memory will employ only two transistors per memory cell, one of which is employed for accessing and the other of which stores the charge. Often "two-rail" logic is used so that a cell C.sub.i,j is provided to store a bit value (data bit b) and a conjugate cell C.sub.i,j is provided to store the opposite bit value b. Because fewer transistors are required in the DRAM memory these memories tend to be used where high information storage density is required while SRAM memory is used where fast access is required.
Because the technology of the DRAM capacitor memory cell differs from that of the SRAM, its failures occur in ways that are entirely different from the way that an SRAM may fail. Because of these differences, some of the testing techniques applicable to SRAMs will not operate satisfactorily with DRAMs. Accordingly, it would be desirable to be able to provide a self-test routine which took into account the different ways that failure can occur in a DRAM so that appropriate remedial measures could be taken.